mitsubishi semiconductor PS21767-V transfer-mold type insulated type aug. 2007 1 PS21767-V integrated power functions 600v/30a low-loss cstbt tm inverter bridge with n-side three-phase output dc-to-ac power conversion application ac100v~200v three-phase inverter drive for small power motor control. fig. 1 package outlines integrated drive, protection and system control functions for upper-leg igbt s : drive circuit, high voltage high-speed level shifting, control supply under-voltage (uv) protection. for lower-leg igbt s : drive circuit, control supply under-voltage protection (uv), short circuit protection (sc). fault signaling : corresponding to an sc fault (lower-leg igbt) or a uv fault (lower-side supply). input interface : 3, 5v line (high active) ? l approved : yellow card no. e80276 dimensions in mm mitsubishi semiconductor PS21767-V transfer-mold type insulated type qr code 1.78 0.2 3.3 0.3 3.3 0.3 6.6 0.3 7.62 0.3 7.62 0.3 7.62 0.3 7.62 0.3 3.95 0.3 2- 3.3 5- 2.2(depth2.6) a = 1.78 0.2 b = 4.32 0.2 2.04 0.3 35.9 0.5 3.1 0.1 (11 1.78) 31 15.5 46 0.2 3.25 0.5 3.3 ( 3.5) ( 3.7) c-c 1.5 1 2 52.5 e b 7.1 12.7 a b a b a b a b 5.6 (2.2) (1.7) (2.8) (13) (12.78) (13.5) f 2 2.2 a 17.7 (1.96) (3.5) (5.5) (1) 1.55 heat sink side 1.5 17.7 0.5 0.5 c c d (2.2) (1.7) terminal code (2.9) (1.75) (1.6) (0.75) (0.6) (0 ~5 ) (1) (1) detail d detail e vufs (upg) vufb vp1 (com) up vvfs (vpg) vvfb vp1 (com) vp vwfs (wpg) vwfb vp1 (com) wp (ung) vno un vn wn fo cfo cin vnc vn1 (wng) (vng) nw nv nu w v u p nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 28 29 30 31 32 33 34 35 36 37 38 27 26 25 24 23 22 21 2019 18 17 16 15 14 13 12 11 10 9 8 76 5 43 2 1 t ype name, lot no. note: all outer lead terminals are with lead free solder (sn-cu) plating.
mitsubishi semiconductor PS21767-V transfer-mold type insulated type aug. 2007 2 note 1 : t c measurement point 400 ?0~+100 ?0~+125 2500 v d = 13.5~16.5v, inverter part t j = 125 c, non-repetitive, less than 2 s (note 1) 60hz, sinusoidal, ac 1 minute, all pins to heat-sink plate v cc(prot) t c t stg v iso v v v v ma v 20 20 ?.5~v d +0.5 ?.5~v d +0.5 1 ?.5~v d +0.5 applied between v p1 -v nc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs applied between u p , v p , w p , u n , v n , w n - v nc applied between f o -v nc sink current at f o terminal applied between cin-v nc control supply voltage control supply voltage input voltage fault output supply voltage fault output current current sensing input voltage v d v db v in v fo i fo v sc 450 500 600 30 60 90.9 ?0~+150 applied between p-nu, nv, nw applied between p-nu, nv, nw t c = 25 c t c = 25 c, less than 1ms t c = 25 c, per 1 chip v cc v cc(surge) v ces i c i cp p c t j condition symbol parameter ratings unit supply voltage supply voltage (surge) collector-emitter voltage each igbt collector current each igbt collector current (peak) collector dissipation junction temperature v v v a a w c maximum ratings (t j = 25 c, unless otherwise noted) inverter part condition symbol parameter ratings unit control (protection) part symbol ratings unit self protection supply voltage limit (short circuit protection capability) module case operation temperature storage temperature isolation voltage v c c v rms to ta l system parameter condition power terminals tc point control terminals igbt chip position fwdi chip position groove 18mm 18mm heat sink side dip-ipm
mitsubishi semiconductor PS21767-V transfer-mold type insulated type aug. 2007 3 2.20 2.30 2.00 1.90 0.80 2.10 0.55 1 10 1.1 2.8 ma v t j = 25 c t j = 125 c i c = 30a, t j = 25 c i c = 30a, t j = 125 c v ce(sat) v ec t on t rr t c(on) t off t c(off) i ces condition symbol parameter limits inverter igbt part (per 1/6 module) inverter fwd part (per 1/6 module) r th(j-c)q r th(j-c)f min. thermal resistance t yp. max. unit t j = 25 c, ? c = 30a, v in = 0v condition symbol parameter limits min. t yp. max. 0.70 unit electrical characteristics (t j = 25 c, unless otherwise noted) inverter part collector-emitter saturation voltage fwdi forward voltage junction to case thermal resistance (note 2) v d = v db = 15v v in = 5v switching times v cc = 300v, v d = v db = 15v i c = 30a, t j = 125 c, v in = 0 ? 5v inductive load (upper-lower arm) collector-emitter cut-off current v ce = v ces 1.70 1.80 1.50 1.30 0.30 0.50 1.50 0.35 v s s s s s c/w c/w control (protection) part note 3 : short circuit protection is functioning only at the low-arms. please select the external shunt resistance such that the sc trip -level is less than 2.0 times of the current rating. 4: fault signal is output when the low-arms short circuit or control supply under-voltage protective functions works. the fault ou tput pulse- width t fo depends on the capacitance of c fo according to the following approximate equation : c fo = 12.2 ? 10 -6 ? t fo [f]. symbol i d v foh v fol v sc(ref) i in uv dbt uv dbr uv dt uv dr t fo v th(on) v th(off) v th(hys) parameter condition limits unit circuit current fault output voltage short circuit trip level control supply under-voltage protection fault output pulse width on threshold voltage off threshold voltage on/off threshold hysteresis voltage v d = v db = 15v v in = 5v t otal of v p1 -v nc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs v sc = 0v, f o terminal pull-up to 5v with 10k ? v sc = 1v, i fo = 1ma t j = 25 c, v d = 15v (note 3) v in = 5v t rip level reset level t rip level reset level c fo = 22nf (note 4) applied between u p , v p , w p , u n , v n , w n -v nc 4.9 0.43 1.0 10.0 10.5 10.3 10.8 1.0 0.8 0.5 0.48 1.5 1.8 2.3 1.4 0.9 7.00 0.55 7.00 0.55 0.95 0.53 2.0 12.0 12.5 12.5 13.0 2.6 min. typ. max. ma ma ma ma v v v ma v v v v ms v v v v d = v db = 15v v in = 0v t otal of v p1 -v nc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs t j 125 c note 2 : grease with good thermal conductivity should be applied evenly with about +100 m~+200 m on the contacting surface of dip-ipm and heat-sink. the contacting thermal resistance between dip-ipm case and heat sink (r th(c-f) ) is determined by the thickness and the thermal con- ductivity of the applied grease. for reference, r th(c-f) (per 1/6 module) is about 0.3 c/w when the grease thickness is 20 m and the thermal conductivity is 1.0w/m? input current
mitsubishi semiconductor PS21767-V transfer-mold type insulated type aug. 2007 4 note 5 : flatness measurement position mounting screw : m3 condition parameter limits mounting torque w eight heat-sink flatness min. mechanical characteristics and ratings t yp. max. 0.59 ?0 unit 21 0.98 100 n? g m recommended : 0.78 n? ( note 5 ) v v v v/ s s khz arms s v c supply voltage control supply voltage control supply voltage control supply variation arm shoot-through blocking time pwm input frequency output r.m.s. current minimum input pulse width v nc voltage variation junction temperature applied between p-nu, nv, nw applied between v p1 -v nc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs for each input signal, t c 100 c t c 100 c, t j 125 c v cc = 300v, v d = v db = 15v, p .f = 0.8, sinusoidal pwm t c 100 c, t j 125 c (note 6) (note 7) 200 v cc 350v, 13.5 v d 16.5v, 13.0 v db 18.5v, ?0 c t c 100 c, n-line wiring inductance less than 10nh (note 8) between v nc -nu, nv, nw (including surge) 400 16.5 18.5 1 20 21 16 5.0 125 v cc v d v db ? v d , ? v db t dead f pwm i o pwin(on) pwin(off) v nc t j condition symbol parameter recommended value min. t yp. max. 0 13.5 13.0 ? 2 0.3 1.6 3.3 3.9 ?.0 ?0 unit recommended operation conditions 300 15.0 15.0 note 6 : the allowable r.m.s. current value depends on the actual application conditions. 7: input signal with on pulse width less than pwin(on) might make no response. 8: ipm might make delayed response (less than about 2 sec) or no response for the input signal with off pulse width less than pwin(off). please refer fig. 2 about delayed response and fig. 6 about n-line inductance. f pwm = 5khz f pwm = 15khz below rated current between rated current and 1.7 times of rated current between 1.7 times and 2.0 times of rated current heat sink side measurement position 3mm heat sink side + +
mitsubishi semiconductor PS21767-V transfer-mold type insulated type aug. 2007 5 fig. 2 about delayed response against shorter input off signal than pwin (off) (p side only) fig. 3 the dip-ipm internal circuit t1 t2 real line ... off pulse width > pwin(off) : turn on time t1 broken line ... off pulse width < pwin(off) : turn on time t2 p side control input internal igbt gate output current ic dip-ipm u out v out w out v no cfo gnd w n v n u n v cc hvic3 hvic2 hvic1 lvic cfo cin cin v no w v u p ho in com v b v s v cc ho in com v b v s v cc ho in com v b v s v cc w n v n u n v p v p u p v nc v n1 v p1 v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb igbt1 igbt2 igbt3 igbt4 igbt5 igbt6 di1 di2 di3 di4 di5 di6 nu nv nw fo fo
mitsubishi semiconductor PS21767-V transfer-mold type insulated type aug. 2007 6 fault output fo output current ic control supply voltage v d protection circuit state control input b1 b2 b3 b4 b5 reset reset uv dt uv dr set b6 b7 protection circuit state lower-arms control input fault output fo sense voltage of the shunt resistor output current ic internal igbt gate sc reference voltage cr circuit time constant delay a5 a8 a4 a3 a1 a2 sc reset set a7 a6 fig. 4 timing charts of the dip-ipm protective functions [a] short-circuit protection (lower-arms only with the external shunt resistor and cr filter) a1. normal operation : igbt on and carrying current. a2. short circuit current detection (sc trigger). a3. igbt gate hard interruption. a4. igbt turns off. a5. f o timer operation starts : the pulse width of the f o signal is set by the external capacitor c fo . a6. input ??: igbt off. a7. input ? a8. igbt off state in spite of input ?? [b] under-voltage protection (lower-arm, uv d ) b1. control supply voltage rising : after the voltage level reaches uv dr , the circuits start to operate when next input is applied. b2. normal operation : igbt on and carrying current. b3. under voltage trip (uv dt ). b4. igbt turns off in spite of control input condition. b5. f o operation starts. b6. under voltage reset (uv dr ). b7. normal operation : igbt on and carrying current.
mitsubishi semiconductor PS21767-V transfer-mold type insulated type aug. 2007 7 mcu 10k ? u p ,v p ,w p ,u n ,v n ,w n v nc (logic) fo dip-ipm 5v line [c] under-voltage protection (upper-arm, uv db ) c1. control supply voltage rises : after the voltage level reaches uv dbr , the circuits start to operate. c2. protection circuit state reset : igbt on and carrying current. c3. normal operation : igbt on and carrying current. c4. under-voltage trip (uv dbt ). c5. igbt off inspite of control input condition, but there is no f o signal output. c6. under-voltage reset (uv dbr ). c7. normal operation : igbt on and carrying current. fig. 5 recommended mcu i/o interface circuit note : rc coupling at each input (parts shown dotted) may change depending on the pwm control scheme used in the application and the wiring impedance of the application s printed circuit board. the dip-ipm input signal section integrates a 2.5k ? (min) pull-down resistor. therefore, when using a external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. fig. 6 recommended wiring around the shunt resistor control input protection circuit state control supply voltage v db output current ic fault output fo high-level (no fault output) uv dbr reset set reset uv dbt c1 c3 c4 c5 c6 c7 c2 nw v nc nv nu dip-ipm the gnd wiring from v no , v nc should be as close to the shunt resistors as possible v no each wiring inductance should be less than 10nh shunt resistor equivalent to the inductance of a copper pattern in dimension of width=3mm, thickness=100 m, length=17mm
mitsubishi semiconductor PS21767-V transfer-mold type insulated type aug. 2007 8 note 1 : input drive is high-active type. there is a 2.5k ? (min.) pull-down resistor integrated in the ic input circuit. to prevent malfunction, the wiring of each in- put should be as short as possible. when using rc coupling circuit, make sure the input signal level meet the turn-on and turn- off threshold voltage. 2: thanks to hvic inside the module, direct coupling to mcu without any opto-coupler or transformer isolation is possible. 3: f o output is open drain type. it should be pulled up to the positive side of a 5v power supply by a resistor of about 10k ? . f o output pulse width is determined by the external capacitor (c fo ) between cfo and v nc terminals (e.g c fo = 22nf t fo = 1.8ms (typ.)) 4: to prevent erroneous protection, the wiring of a, b should be as short as possible. 5: the time constant r1c5 of the protection circuit should be selected in the range of 1.5-2 s. sc interrupting time might vary with the wiring pattern. tight tolerance, temp-compensated type is recommended for r1, c5. 6: all capacitors should be mounted as close to the terminals of the dip-ipm as possible. (c1: good temperature, frequency charact er- istic electrolytic type, and c2, c3: good temperature, frequency and dc bias characteristic ceramic type are recommended.) 7: to prevent surge destruction, the wiring between the smoothing capacitor and the p, n1 terminals should be as short as possible . generally a 0.1-0.22 f snubber between the p-n1 terminals is recommended. 8: it is recommended to insert a zener diode (24v/1w) between each pair of control supply terminals to prevent surge destruction. 9: if control gnd is connected to power gnd by broad pattern, it may cause malfunction by power gnd fluctuation. it is recommended to connect control gnd and power gnd at only a point. 10 : the reference voltage vref of comparator should be set up the same rating of short circuit trip level (vsc(ref): min.0.43v to m ax.0.53v). 11 : or logic output high level should exceed the maximum short circuit trip level (v sc(ref): max.0.53v). fig. 7 typical dip-ipm application circuit example c1: tight tolerance temp-compensated electrolytic type c2,c3: 0.22~2 f r-category ceramic capacitor for noise filtering ho ho dip-ipm c3 c3 c3 c2 c2 c2 c1 c1 c1 in in in com com com u out v out w out cfo v no gnd f o w n v n v cc c a c4(c fo ) cfo cin nw cin v s v s v b v b ho v s v b v cc v cc v cc fo w n v n u n u n w p v p u p v nc v no v n1 v p1 v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb m c3 hvic1 hvic2 hvic3 lvic w v u p c5 r1 b vref + - c5 r1 b vref + - c5 n1 r1 b vref + - 15v line 5v line controller nv nu too long wiring here might cause short-circuit. if this wiring is too long, the sc level fluctuation might be larger and cause sc malfunction. long gnd wiring here might generate noise to input and cause igbt malfunction. comparator external protection circuit shunt resistors or logic
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